The present disclosure relates to Integrated Circuits for current mode logic drivers to improve electrostatic discharge (ESD) protection.
For high-speed differential operation in the GHz range, current mode logic (CML) drivers are typically used for their large attainable bandwidth. These are simple resistively loaded differential amplifiers. As technology scales supply voltage, transistor threshold voltage, breakdown voltage reduces. The lower breakdown voltage of the devices makes them susceptible to the electrostatic discharge (ESD) stress. Lower threshold voltages of the transistors make them conduct large current at small overdrive voltages. This current can exceed the current limit of the salicided driver transistor, leading to failures. Methods are needed for increasing the ESD design window without adding significant ESD device capacitance or area. Unfortunately, decreased ESD window as technology scales smaller leads to increased ESD device area and capacitance. Furthermore, increasing signaling speeds decreases the capacitance budgets at transceivers.
Recently, failure of driver NFETs was discovered in the CML driver topology during pad-to-pad or pad-to-ground electrostatic discharge (ESD) stress. It has been observed that during pad-to-pad ESD stress, one of the driver transistors of the CML driver turns on putting the entire ESD stress across its partner (the other driver transistor of the CML driver). In a CML driver structure, an ESD zap is applied at one pad and ground connection is applied to the other pad to create an ESD stress test. In operation, one of the drivers of the CML driver structure turns on, discharging the current mode (CM) node of the CML driver to 0V. This puts most of the ESD stress on its partner device, which can cause drain-source shorting on the partner driver transistor, leading to ESD failures.
Conventional technologies, such as shown in FIG. 1, provide a circuit that includes an RC clamp. In some prior circuits, such as for ESD protection for high-speed receiver circuits, a biasing circuits attempts to prevent oxide breakdown in a receiver by increasing source impedance. The tail current source may be disabled by the bias network. In another prior circuit that uses biasing to prevent drain breakdown, the circuit increases allowable pad voltages during an output-to-output stress by preventing drain breakdown using a bias network. A problem with this circuit is that it decreases allowable pad voltage for output-to-Vss stress.